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1

[IEEE 2011 IEEE International Symposium on Circuits and Systems (ISCAS) - Rio de Janeiro, Brazil (2011.05.15-2011.05.18)] 2011 IEEE International Symposium of Circuits and Systems (ISCAS) - An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture

Sani, Awais, Coussy, Philippe, Chavet, Cyrille, Martin, Eric

Année:

2011

Langue:

english

Fichier:

PDF, 468 KB

english, 2011

2

[IEEE 2012 IEEE Workshop on Signal Processing Systems (SiPS) - Quebec City, QC, Canada (2012.10.17-2012.10.19)] 2012 IEEE Workshop on Signal Processing Systems - A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders

Sanchez, Oscar, Jezequel, Michel, Rehman, Saeed ur, Sani, Awais, Chavet, Cyrille, Coussy, Philippe, Jego, Christophe

Année:

2012

Langue:

english

Fichier:

PDF, 456 KB

english, 2012

3

[IEEE 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Lisbon, Portugal (2015.5.24-2015.5.27)] 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Improving storage of patterns in recurrent neural networks: Clone-based model and architecture

Wouafo, Hugues, Chavet, Cyrille, Coussy, Philippe

Année:

2015

Langue:

english

Fichier:

PDF, 876 KB

english, 2015

4

[IEEE 2007 IEEE International Symposium on Circuits and Systems - New Orleans, LA, USA (2007.05.27-2007.05.30)] 2007 IEEE International Symposium on Circuits and Systems - A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

Cyrille, Chavet, Philippe, Coussy, Pascal, Urard, Eric, Martin

Année:

2007

Langue:

english

Fichier:

PDF, 1.19 MB

english, 2007

5

[IEEE 2020 IEEE International Symposium on Circuits and Systems (ISCAS) - Sevilla (2020.10.12-2020.10.14)] 2020 IEEE International Symposium on Circuits and Systems (ISCAS) - Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation

Harcha, Ghita, Lapotre, Vianney, Chavet, Cyrille, Coussy, Philippe

Année:

2020

Fichier:

PDF, 1.22 MB

2020

6

A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm

Sani, Awais Hussain, Coussy, Philippe, Chavet, Cyrille

Journal:

IEEE Transactions on Signal Processing

Année:

2013

Langue:

english

Fichier:

PDF, 1.69 MB

english, 2013

7

[IEEE 2007 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA (2007.11.4-2007.11.8)] 2007 IEEE/ACM International Conference on Computer-Aided Design - A design flow dedicated to multi-mode architectures for DSP applications

Chavet, Cyrille, Andriamisaina, Caaliph, Coussy, Philippe, Casseau, Emmanuel, Juin, Emmanuel, Urard, Pascal, Martin, Eric

Année:

2007

Langue:

english

Fichier:

PDF, 886 KB

english, 2007

8

[IEEE 2013 23rd International Conference on Field Programmable Logic and Applications (FPL) - Porto, Portugal (2013.09.2-2013.09.4)] 2013 23rd International Conference on Field programmable Logic and Applications - Dynamic branch prediction for high-level synthesis

Lapotre, Vianney, Coussy, Philippe, Chavet, Cyrille, Wouafo, Hugues, Danilo, Robin

Année:

2013

Langue:

english

Fichier:

PDF, 332 KB

english, 2013

9

[IEEE 2012 15th Euromicro Conference on Digital System Design (DSD) - Cesme, Izmir, Turkey (2012.09.5-2012.09.8)] 2012 15th Euromicro Conference on Digital System Design - OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters

Burgio, Paolo, Marongiu, Andrea, Heller, Dominique, Chavet, Cyrille, Coussy, Philippe, Benini, Luca

Année:

2012

Langue:

english

Fichier:

PDF, 665 KB

english, 2012

10

[IEEE 2010 17th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2010) - Athens, Greece (2010.12.12-2010.12.15)] 2010 17th IEEE International Conference on Electronics, Circuits and Systems - Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach

Sani, Awais, Coussy, Philippe, Chavet, Cyrille, Martin, Eric

Année:

2010

Langue:

english

Fichier:

PDF, 1.25 MB

english, 2010

11

[IEEE 2013 IEEE Workshop on Signal Processing Systems (SiPS) - Taipei City, Taiwan (2013.10.16-2013.10.18)] SiPS 2013 Proceedings - A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller

Briki, Aroua, Chavet, Cyrille, Coussy, Philippe

Année:

2013

Langue:

english

Fichier:

PDF, 449 KB

english, 2013

12

[IEEE ICASSP 2013 - 2013 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) - Vancouver, BC, Canada (2013.05.26-2013.05.31)] 2013 IEEE International Conference on Acoustics, Speech and Signal Processing - On-chip implementation of memory mapping algorithm to support flexible decoder architecture

Rehman, Saeed-ur, Sani, Awais, Coussy, Philippe, Chavet, Cyrille

Année:

2013

Langue:

english

Fichier:

PDF, 195 KB

english, 2013

13

[IEEE ICASSP 2014 - 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) - Florence, Italy (2014.5.4-2014.5.9)] 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) - Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures

Saeed-ur-Rehman,, Sani, Awais, Chavet, Cyrille, Coussy, Philippe

Année:

2014

Langue:

english

Fichier:

PDF, 196 KB

english, 2014

14

[IEEE 2011 IEEE 9th International Conference on ASIC (ASICON 2011) - Xiamen, China (2011.10.25-2011.10.28)] 2011 9th IEEE International Conference on ASIC - High-Level Synthesis: On the path to ESL design

Coussy, Philippe, Heller, Dominique, Chavet, Cyrille

Année:

2011

Langue:

english

Fichier:

PDF, 823 KB

english, 2011

15

Advanced Hardware Design for Error Correcting Codes ||

Chavet, Cyrille, Coussy, Philippe

Année:

2015

Langue:

english

Fichier:

PDF, 6.15 MB

english, 2015

16

[IEEE ICASSP 2011 - 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) - Prague, Czech Republic (2011.05.22-2011.05.27)] 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) - A methodology based on Transportation problem modeling for designing parallel interleaver architectures

Sani, Awais, Coussy, Philippe, Chavet, Cyrille, Martin, Eric

Année:

2011

Langue:

english

Fichier:

PDF, 180 KB

english, 2011

17

[ACM Press the 23rd ACM international conference - Paris, France (2013.05.02-2013.05.03)] Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI '13 - A memory mapping approach for network and controller optimization in parallel interleaver architectures

Briki, Aroua, Chavet, Cyrille, Coussy, Philippe

Année:

2013

Langue:

english

Fichier:

PDF, 580 KB

english, 2013

18

[ACM Press the 17th great lakes symposium - Stresa-Lago Maggiore, Italy (2007.03.11-2007.03.13)] Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07 - A design methodology for space-time adapter

Chavet, Cyrille, Coussy, Philippe, Urard, Pascal, Martin, Eric

Année:

2007

Langue:

english

Fichier:

PDF, 542 KB

english, 2007

19

[ACM Press the great lakes symposium - Salt Lake City, Utah, USA (2012.05.03-2012.05.04)] Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 - A design approach dedicated to network-based and conflict-free parallel interleavers

Briki, Aroua, Chavet, Cyrille, Coussy, Philippe, Martin, Eric

Année:

2012

Langue:

english

Fichier:

PDF, 427 KB

english, 2012

20

[ACM Press the 24th edition of the great lakes symposium - Houston, Texas, USA (2014.05.21-2014.05.23)] Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14 - A memory mapping approach based on network customization to design conflict-free parallel hardware architectures

Ur Reehman, Saeed, chavet, Cyrille, Coussy, Philippe

Année:

2014

Langue:

english

Fichier:

PDF, 592 KB

english, 2014

21

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

Coussy, Philippe, Chavet, Cyrille, Wouafo, Hugues Nono, Conde-Canencia, Laura

Journal:

ACM Journal on Emerging Technologies in Computing Systems

Année:

2015

Langue:

english

Fichier:

PDF, 6.29 MB

english, 2015

22

[IEEE 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) - Marseille, France (2014.12.7-2014.12.10)] 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) - A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code

Lanoe, Mickael, Bordin, Matteo, Heller, Dominique, Coussy, Philippe, Chavet, Cyrille

Année:

2014

Langue:

english

Fichier:

PDF, 292 KB

english, 2014

23

[IEEE Conference Publications Design, Automation and Test in Europe - Grenoble, France (2015.03.9-2015.03.13)] Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 - In-Place Memory Mapping Approach for Optimized Parallel Hardware Interleaver Architectures

Reehman, Saeed Ur, Chavet, Cyrille, Coussy, Philippe, Sani, Awais

Année:

2015

Langue:

english

Fichier:

PDF, 185 KB

english, 2015

24

[IEEE 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Rennes, France (2016.10.12-2016.10.14)] 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection

Danilo, Robin, Wouafo, Hugues Nono, Chavet, Cyrille, Gripon, Vincent, Conde-Canencia, Laura, Coussy, Philippe

Année:

2016

Langue:

english

Fichier:

PDF, 6.10 MB

english, 2016

25

[IEEE 2017 IEEE International Workshop on Signal Processing Systems (SiPS) - Lorient (2017.10.3-2017.10.5)] 2017 IEEE International Workshop on Signal Processing Systems (SiPS) - Efficient scalable hardware architecture for highly performant encoded neural networks

Wouafo, Hugues, Chavet, Cyrille, Coussy, Philippe, Danilo, Robin

Année:

2017

Langue:

english

Fichier:

PDF, 554 KB

english, 2017

26

Clone-Based Encoded Neural Networks to Design Efficient Associative Memories

Wouafo, Hugues, Chavet, Cyrille, Coussy, Philippe

Journal:

IEEE Transactions on Neural Networks and Learning Systems

Année:

2019

Fichier:

PDF, 11 KB

2019

27

[IEEE ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) - Barcelona, Spain (2020.5.4-2020.5.8)] ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) - Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards

Harb, Hassan, Chavet, Cyrille

Année:

2020

Fichier:

PDF, 450 KB

2020

28

Fully Parallel Circular-Shift Rotation Network for Communication Standards

Harb, Hassan, Chavet, Cyrille

Journal:

IEEE Transactions on Circuits and Systems II: Express Briefs

Année:

2020

Fichier:

PDF, 591 KB

2020